Traffic-Aware Energy-Efficient Hybrid Input Buffer Design for On-Chip Routers

Abstract

A growing number of cores per chip has driven the rapid adoption of increasingly complex Networks-on-Chip (NoCs) under diminishing power budgets. In such a situation, having more routers or having routers with higher radix is inevitable, which creates higher demands for input buffers while they already draw a significant amount of power. Thus, this paper introduces a hybrid input buffer design for on-chip routers attempting to shrink their power consumption while conserving performance. The key idea behind this proposal is to design input buffers with the network traffic characteristics in mind. As in our observations, a large portion of the network traffic is short packets, which means, it is fair to implement most of the input buffers with slow but less leaky devices (STT-MRAM) to suppress the static power consumption while still having most of the network traffic stored in fast but leaky SRAM devices to conserve the network performance. Our evaluations show that this hybrid design can achieve an average reduction of energy consumption per flit by 44.5% under 93.6% of the original router area and small degradation of the network performance.