Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester

Abstract

This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets, examining testability of our processor, or developing test procedures for it. We first choose our CUT as a version of RISCV and explain its ISA and eventually its RTL architecture. Various test techniques for this processor are studied, and then we will choose the IEEE Std.1149.1 for insertion into our processor and developing a virtual tester to interact with the test-ready processor model.