Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505064
A. Cilardo
Security is an important driver for the evolution of the RISC-V architecture. Several initiatives aim at exploiting the privileged architecture and the Physical Memory Protection mechanisms foreseen by the RISC-V specification as a foundation for robust trusted execution environments. This short paper introduces a memory encryption unit fitting the organization of the RISC-V privileged architecture. The unit is suitable for very resource-constrained systems and is mainly targeted at FPGA devices. The design relies on a flexible and efficient stream cipher, the ChaCha algorithm. The work presents an overview of the system architecture and the detail of the FPGA-based implementation of the memory encryption unit, along with some experimental evaluation and comparisons with state-of-the-art contributions.
{"title":"Memory Encryption Support for an FPGA-based RISC-V Implementation","authors":"A. Cilardo","doi":"10.1109/DTIS53253.2021.9505064","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505064","url":null,"abstract":"Security is an important driver for the evolution of the RISC-V architecture. Several initiatives aim at exploiting the privileged architecture and the Physical Memory Protection mechanisms foreseen by the RISC-V specification as a foundation for robust trusted execution environments. This short paper introduces a memory encryption unit fitting the organization of the RISC-V privileged architecture. The unit is suitable for very resource-constrained systems and is mainly targeted at FPGA devices. The design relies on a flexible and efficient stream cipher, the ChaCha algorithm. The work presents an overview of the system architecture and the detail of the FPGA-based implementation of the memory encryption unit, along with some experimental evaluation and comparisons with state-of-the-art contributions.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128986971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505096
P. Inglese, E. Vatajelu, G. D. Natale
Emerging non-volatile memories are widely studied today as means to maximize energy efficiency and because they enable the so-called Computation-In-Memory. The Logic-inMemory (LIM) paradigm is a subset of the Computation-inMemory and it focuses on the execution of Boolean operations inside the memory. Among the most popular solutions, MAGIC and FELIX promise non-input destructive operations, as classical computation paradigms, allowing therefore to re-use the set of input data for several operations. In this paper we have analyzed the electrical behavior of some significant LIM implementations (MAGIC NOR and FELIX NAND) under various operation conditions. Our results show that it is not trivial to guarantee noninput destructive operations (in the case of FELIX NAND) and there is a real difficulty in concatenating several operations due to non-ideal intermediate results.
{"title":"On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions","authors":"P. Inglese, E. Vatajelu, G. D. Natale","doi":"10.1109/DTIS53253.2021.9505096","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505096","url":null,"abstract":"Emerging non-volatile memories are widely studied today as means to maximize energy efficiency and because they enable the so-called Computation-In-Memory. The Logic-inMemory (LIM) paradigm is a subset of the Computation-inMemory and it focuses on the execution of Boolean operations inside the memory. Among the most popular solutions, MAGIC and FELIX promise non-input destructive operations, as classical computation paradigms, allowing therefore to re-use the set of input data for several operations. In this paper we have analyzed the electrical behavior of some significant LIM implementations (MAGIC NOR and FELIX NAND) under various operation conditions. Our results show that it is not trivial to guarantee noninput destructive operations (in the case of FELIX NAND) and there is a real difficulty in concatenating several operations due to non-ideal intermediate results.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127755278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505078
Cédric Marchand, I. O’Connor, Mayeul Cantan, E. Breyer, S. Slesazeck, T. Mikolajick
Emerging non-volatile memories are getting new interest in the system design community. They are used to design logic-in-memory circuits and propose alternatives to von-Neuman architectures. Hafnium oxide-based based ferroelectric memory technology, which is fully compatible with CMOS technologies is particularly interesting for logic-in-memory designs. Indeed, this compatibility leads to various possibilities for fine-grain logic in memory applications where the memory capable element is tightly integrated with the transistors in the system. Nonvolatile and energy efficient computing for Internet of things and embedded artificial intelligence are among the potential applications for this technology.In this article, we focus on ferroelectric field-effect transistors (FeFET) and present an overview of three different fine-grain logic-in-memory possibilities with FeFETs: custom operation designs, reconfigurable circuits and a hybrid memory element accessible by content or by address. All presented circuits have been designed within a test chip using 28nm technology provided by GLOBALFOUNDRIES.
{"title":"FeFET based Logic-in-Memory: an overview","authors":"Cédric Marchand, I. O’Connor, Mayeul Cantan, E. Breyer, S. Slesazeck, T. Mikolajick","doi":"10.1109/DTIS53253.2021.9505078","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505078","url":null,"abstract":"Emerging non-volatile memories are getting new interest in the system design community. They are used to design logic-in-memory circuits and propose alternatives to von-Neuman architectures. Hafnium oxide-based based ferroelectric memory technology, which is fully compatible with CMOS technologies is particularly interesting for logic-in-memory designs. Indeed, this compatibility leads to various possibilities for fine-grain logic in memory applications where the memory capable element is tightly integrated with the transistors in the system. Nonvolatile and energy efficient computing for Internet of things and embedded artificial intelligence are among the potential applications for this technology.In this article, we focus on ferroelectric field-effect transistors (FeFET) and present an overview of three different fine-grain logic-in-memory possibilities with FeFETs: custom operation designs, reconfigurable circuits and a hybrid memory element accessible by content or by address. All presented circuits have been designed within a test chip using 28nm technology provided by GLOBALFOUNDRIES.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117301231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505098
P. Habiby, S. Huhn, R. Drechsler
The IEEE 1687 Std. provides an efficient access methodology for embedded instruments in complex system-on-a-chip designs by introducing reconfigurable scan networks. This flexibility enables the reduction of the overall test access time, which significantly decreases the test costs compared to the conventional daisy-chaining method. However, the new access methodology strictly requires effective test schedulers that consider multi-power domains with individual constraints.This work proposes a novel test scheduler that orchestrates the Boolean Satisfiability problem in conjunction with Pseudo-Boolean optimization techniques. The effectiveness of the proposed scheduler is proven by considering networks with over one thousand of so-called instruments forming industrial representative benchmark candidates.
{"title":"Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability","authors":"P. Habiby, S. Huhn, R. Drechsler","doi":"10.1109/DTIS53253.2021.9505098","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505098","url":null,"abstract":"The IEEE 1687 Std. provides an efficient access methodology for embedded instruments in complex system-on-a-chip designs by introducing reconfigurable scan networks. This flexibility enables the reduction of the overall test access time, which significantly decreases the test costs compared to the conventional daisy-chaining method. However, the new access methodology strictly requires effective test schedulers that consider multi-power domains with individual constraints.This work proposes a novel test scheduler that orchestrates the Boolean Satisfiability problem in conjunction with Pseudo-Boolean optimization techniques. The effectiveness of the proposed scheduler is proven by considering networks with over one thousand of so-called instruments forming industrial representative benchmark candidates.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132031422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets, examining testability of our processor, or developing test procedures for it. We first choose our CUT as a version of RISCV and explain its ISA and eventually its RTL architecture. Various test techniques for this processor are studied, and then we will choose the IEEE Std.1149.1 for insertion into our processor and developing a virtual tester to interact with the test-ready processor model.
{"title":"Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester","authors":"Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Z. Navabi","doi":"10.1109/DTIS53253.2021.9505110","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505110","url":null,"abstract":"This paper is on a RISCV-like processor and developing a virtual tester for it. We define a Virtual Tester as a testbench in an HDL that performs test functions as an automatic test equipment does. The virtual tester is used for developing test sets, examining testability of our processor, or developing test procedures for it. We first choose our CUT as a version of RISCV and explain its ISA and eventually its RTL architecture. Various test techniques for this processor are studied, and then we will choose the IEEE Std.1149.1 for insertion into our processor and developing a virtual tester to interact with the test-ready processor model.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132239402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505093
Romeric Gay, V. D. Marca, H. Aziza, A. Régnier, S. Niel, A. Marzaki
This paper addresses the design and characterization of different architectures of novels high-density multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.
{"title":"Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology","authors":"Romeric Gay, V. D. Marca, H. Aziza, A. Régnier, S. Niel, A. Marzaki","doi":"10.1109/DTIS53253.2021.9505093","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505093","url":null,"abstract":"This paper addresses the design and characterization of different architectures of novels high-density multi-gate transistors manufactured in a 40 nm embedded Non-Volatile Memory technology. The proposed multi-gate architectures are based on vertical transistors integrated in deep trenches built alongside the main transistor. Thanks to the built-in trench, the proposed manufacturing process increases the transistor width without impacting its footprint. The electrical behaviour of the different multi-gate transistor architectures is studied and compared based on I-V characteristics. Relevant physical and electrical parameters such as the device footprint, the ON and OFF currents along with the threshold voltage and subthreshold slopes are extracted in order to determine the best candidate among the three studied architectures.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129279322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505085
F. Matteo, R. Simola, Franck Melul, K. Coulié, J. Postel-Pellerin, A. Régnier
The Electrically Erasable Programmable Read Only Memory (EEPROM) technology has been widely studied but EEPROM Technology Computer Aided-Design (TCAD) simulations still need to be improved to handle the rises of the quality requirements of the semiconductor market. In this paper, the impact of endurance degradation on EEPROM programming window and the corresponding TCAD simulation are investigated. Advanced calibrated TCAD simulation on 110nm node is used to evaluate the distribution of negative charges trapped in the tunnel (bulk) oxide during EEPROM cycling. The total negative charge evolution found by our simulation is in agreement with the well-known trapping power law found in the literature.
{"title":"Simulation of state of the art EEPROM programming window closure during endurance degradation","authors":"F. Matteo, R. Simola, Franck Melul, K. Coulié, J. Postel-Pellerin, A. Régnier","doi":"10.1109/DTIS53253.2021.9505085","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505085","url":null,"abstract":"The Electrically Erasable Programmable Read Only Memory (EEPROM) technology has been widely studied but EEPROM Technology Computer Aided-Design (TCAD) simulations still need to be improved to handle the rises of the quality requirements of the semiconductor market. In this paper, the impact of endurance degradation on EEPROM programming window and the corresponding TCAD simulation are investigated. Advanced calibrated TCAD simulation on 110nm node is used to evaluate the distribution of negative charges trapped in the tunnel (bulk) oxide during EEPROM cycling. The total negative charge evolution found by our simulation is in agreement with the well-known trapping power law found in the literature.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117098855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505074
Ihab Alshaer, Brice Colombier, C. Deleuze, V. Beroulle, P. Maistri
Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.
{"title":"Microarchitecture-aware Fault Models: Experimental Evidence and Cross-Layer Inference Methodology","authors":"Ihab Alshaer, Brice Colombier, C. Deleuze, V. Beroulle, P. Maistri","doi":"10.1109/DTIS53253.2021.9505074","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505074","url":null,"abstract":"Fault injection attacks are considered one of the major threats to cyber-physical systems. The increasing complexity of embedded microprocessors involves complicated behaviours in presence of such attacks. Realistic fault models are required to study code vulnerabilities and be able to protect digital systems from these attacks. However, inferring fault models using only limited observations of faulty microprocessors is difficult. In this article, we present experiments that show the difficulty of characterizing and modelling the fault injection effects. From there, we propose a complete approach for fault analysis to build proper fault models at different system levels, which will help in designing suitable countermeasures at reasonable cost.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116584044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505051
Abdullah Aljuffri, C. Reinbrecht, S. Hamdioui, M. Taouil
Power-based side channel attacks (SCAs) are recognized as a powerful type of hardware attacks. Recently, attacks based on deep learning (DL) neural networks have become popular due to their high efficiency. However, even these attacks face problems when sophisticated countermeasures exist. Pre-processing the input data is an effective way to improve the performance of such neural networks. Currently, only limited research has focused on exploring pre-processing techniques for DL-based attacks. In this paper, we propose to the best of our knowledge for the first time the usage of data transformation, data concatenation and stacked auto-encoder (encoder only) as pre-processing methods. Thereafter, we compare them with the existing techniques, namely data augmentation and stacked auto-encoder techniques. Our results show that the data transformation technique achieves the best results from the evaluated methods; it improves the validation accuracy from 75% to 95% and 23% to 26% for the RSA and AES implementations, respectively.
{"title":"Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks","authors":"Abdullah Aljuffri, C. Reinbrecht, S. Hamdioui, M. Taouil","doi":"10.1109/DTIS53253.2021.9505051","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505051","url":null,"abstract":"Power-based side channel attacks (SCAs) are recognized as a powerful type of hardware attacks. Recently, attacks based on deep learning (DL) neural networks have become popular due to their high efficiency. However, even these attacks face problems when sophisticated countermeasures exist. Pre-processing the input data is an effective way to improve the performance of such neural networks. Currently, only limited research has focused on exploring pre-processing techniques for DL-based attacks. In this paper, we propose to the best of our knowledge for the first time the usage of data transformation, data concatenation and stacked auto-encoder (encoder only) as pre-processing methods. Thereafter, we compare them with the existing techniques, namely data augmentation and stacked auto-encoder techniques. Our results show that the data transformation technique achieves the best results from the evaluated methods; it improves the validation accuracy from 75% to 95% and 23% to 26% for the RSA and AES implementations, respectively.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"366 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116390199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-28DOI: 10.1109/DTIS53253.2021.9505067
W. Ruggeri, P. Bernardi, S. Littardi, M. Reorda, D. Appello, C. Bertani, G. Pollaccia, V. Tancorre, R. Ugioli
Burn-In equipment provide both external and internal stress to the device under test. External stress, such as thermal stress, is provided by a climatic chamber or by socket-level local temperature forcing tools, and aims at aging the circuit material, while internal stress, such as electrical stress, consists in driving the circuit nodes to produce a high internal activity. To support internal stress, Burn-In test equipment is usually characterized by large memory capabilities required to store precomputed patterns that are then sequenced to the circuit inputs. Because of the increasing complexity and density of the new generations of SoCs, evaluating the effectiveness of the patterns applied to a Device under Test (DUT) through a simulation phase requires long periods of time. Moreover, topology-related considerations are becoming more and more important in modern high-density designs, so a way to include this information into the evaluation has to be devised. In this paper we show a feasible solution to this problem: the idea is to load in the DUT a pattern not by shifting inside of it a bit at a time but loading the entire pattern at once inside of it; this kind of procedure allows for conservative stress measures, thus it fits for stress analysis purposes. Moreover, a method to take the topology of the DUT into account when calculating the activity metrics is proposed, so to obtain stress metrics which can better represent the activity a circuit is subject to. An automotive chip accounting for about 20 million of gates is considered as a case of study. Resorting to it we show both the feasibility and the effectiveness of the proposed methodology.
{"title":"Innovative methods for Burn-In related Stress Metrics Computation","authors":"W. Ruggeri, P. Bernardi, S. Littardi, M. Reorda, D. Appello, C. Bertani, G. Pollaccia, V. Tancorre, R. Ugioli","doi":"10.1109/DTIS53253.2021.9505067","DOIUrl":"https://doi.org/10.1109/DTIS53253.2021.9505067","url":null,"abstract":"Burn-In equipment provide both external and internal stress to the device under test. External stress, such as thermal stress, is provided by a climatic chamber or by socket-level local temperature forcing tools, and aims at aging the circuit material, while internal stress, such as electrical stress, consists in driving the circuit nodes to produce a high internal activity. To support internal stress, Burn-In test equipment is usually characterized by large memory capabilities required to store precomputed patterns that are then sequenced to the circuit inputs. Because of the increasing complexity and density of the new generations of SoCs, evaluating the effectiveness of the patterns applied to a Device under Test (DUT) through a simulation phase requires long periods of time. Moreover, topology-related considerations are becoming more and more important in modern high-density designs, so a way to include this information into the evaluation has to be devised. In this paper we show a feasible solution to this problem: the idea is to load in the DUT a pattern not by shifting inside of it a bit at a time but loading the entire pattern at once inside of it; this kind of procedure allows for conservative stress measures, thus it fits for stress analysis purposes. Moreover, a method to take the topology of the DUT into account when calculating the activity metrics is proposed, so to obtain stress metrics which can better represent the activity a circuit is subject to. An automotive chip accounting for about 20 million of gates is considered as a case of study. Resorting to it we show both the feasibility and the effectiveness of the proposed methodology.","PeriodicalId":435982,"journal":{"name":"2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)","volume":"117 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133864441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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