A novel clocking strategy for dynamic circuits

Abstract

This paper proposes a new clocking strategy for dynamic circuits. It provides faster performance and smaller area than conventional clocking schemes. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit carry look ahead adder (CLA) is designed and simulated using 0.25 /spl mu/m CMOS technology to demonstrate 32.7% faster speed than the conventional clocking scheme and 19.4% transistor counter reduction.