Operational simulation of an x-ray lithography cell: comparison of 200mm and 300mm wafers

Abstract

We review progress on a project to evaluate prospective operations in a semiconductor wafer fab that employs next generation, proximity X-ray lithography to pattern the critical dimensions of computer chips. A simulation model is developed that captures the processing of wafers through an X-ray lithography cell using a synchrotron as the source of exposure radiation. The model incorporates the best current information on unit-cell design and processing times and implements a range of events that interrupt the flow of wafers processing on the cell. Performance measures estimated from the simulation include the weekly throughput for the cell and the frequency of SEMI E-10 equipment states for the corresponding exposure tool. Simulation experiments are conducted to compare the performance of a cell fabricating 200 mm wafers with that of a cell fabricating 300 mm wafers, for each of three different chip sizes. Results illustrate the anticipated dependence of average wafer throughput on wafer size and assumptions regarding the number of chips per wafer, with a maximum of approximately 3400 wafers/week for 200 mm wafers with 25/spl times/25 mm field size. Ignoring wafer-sort losses, however, a maximum throughput of approximately 410,000 chips/week is realized for 300 mm wafers with 11/spl times/22 mm fields. Remarkably, the distribution of equipment states remains relatively unchanged across simulation experiments.