{"title":"ESD Protection Reliability in 1μM CMOS Technologies","authors":"C. Duvvury, R. A. McPhee, D. Baglee, R. Rountree","doi":"10.1109/IRPS.1986.362134","DOIUrl":null,"url":null,"abstract":"The use of graded drains and silicided diffusions are shown to severely degrade Electrostatic Protection circuits when compared to their performance with traditional processing technology. The impact of each of these process options on the protection circuit sizing and the particular failure modes observed are reported here.","PeriodicalId":354436,"journal":{"name":"24th International Reliability Physics Symposium","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1986-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"44","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"24th International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.1986.362134","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 44
Abstract
The use of graded drains and silicided diffusions are shown to severely degrade Electrostatic Protection circuits when compared to their performance with traditional processing technology. The impact of each of these process options on the protection circuit sizing and the particular failure modes observed are reported here.
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