G. Wang, Zhang Tiefei, Like Yan, Xie Bin, Tianzhou Chen
{"title":"The Design of a Cycle Accurate Multi-core Architecture Performance Simulator","authors":"G. Wang, Zhang Tiefei, Like Yan, Xie Bin, Tianzhou Chen","doi":"10.1109/SEC.2008.19","DOIUrl":null,"url":null,"abstract":"As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 Fifth IEEE International Symposium on Embedded Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SEC.2008.19","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
As multi-core technology has become the trend to improve the performance of processor, there is more need to design a performance simulator for the design of multi-core architecture and for the evaluation of system performance. However there are few simulators that support different architectures of multi-core processor well. This paper presents a design and implementation of a cycle accurate multi-core processor architecture simulator, it is a component design, which can be customized to different multi-core architectures, furthermore, provides a practical tool for the design and evaluation of multi-core architecture.
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