Implementation of a streaming execution unit

D. Cheresiz, B. Juurlink, S. Vassiliadis, H. Wijshoff
{"title":"Implementation of a streaming execution unit","authors":"D. Cheresiz, B. Juurlink, S. Vassiliadis, H. Wijshoff","doi":"10.1109/DSD.2002.1115364","DOIUrl":null,"url":null,"abstract":"The Complex Streamed Instruction (CSI) set is an ISA extension targeted at multimedia applications. CSI instructions process two-dimensional data streams stored in memory, performing sectioning, data alignment and conversion between different packed data types all in hardware. It has been shown previously that CSI provides significant speedups compared to current media ISA extensions such as MMX and VIS. This paper presents a detailed design of a unit that can execute CSI instructions under the assumption that the unit is interfaced with the L1 data cache. In particular it is shown that the complex, two-dimensional, address-generation calculations can be performed in a pipelined fashion and implemented using a three-stage pipeline with acceptable delay and hardware cost.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2002.1115364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

The Complex Streamed Instruction (CSI) set is an ISA extension targeted at multimedia applications. CSI instructions process two-dimensional data streams stored in memory, performing sectioning, data alignment and conversion between different packed data types all in hardware. It has been shown previously that CSI provides significant speedups compared to current media ISA extensions such as MMX and VIS. This paper presents a detailed design of a unit that can execute CSI instructions under the assumption that the unit is interfaced with the L1 data cache. In particular it is shown that the complex, two-dimensional, address-generation calculations can be performed in a pipelined fashion and implemented using a three-stage pipeline with acceptable delay and hardware cost.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
流执行单元的实现
复杂流指令(CSI)集是针对多媒体应用的ISA扩展。CSI指令处理存储在内存中的二维数据流,在硬件中执行不同封装数据类型之间的切片、数据对齐和转换。先前已经证明,与当前的媒体ISA扩展(如MMX和VIS)相比,CSI提供了显著的加速。本文给出了一个可以执行CSI指令的单元的详细设计,假设该单元与L1数据缓存接口。特别是,它显示了复杂的二维地址生成计算可以以流水线方式执行,并使用具有可接受的延迟和硬件成本的三阶段流水线实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
相关文献
Chronic conditions, disability, and quality of life in older adults with multimorbidity in Spain
IF 8 2区 医学European Journal of Internal MedicinePub Date : 2015-04-01 DOI: 10.1016/j.ejim.2015.02.016
Maria João Forjaz , Carmen Rodriguez-Blazquez , Alba Ayala , Vicente Rodriguez-Rodriguez , Jesús de Pedro-Cuesta , Susana Garcia-Gutierrez , Alexandra Prados-Torres
Functional disability and social participation restriction associated with chronic conditions in middle-aged and older adults
IF 0 Journal of Epidemiology & Community HealthPub Date : 2016-10-17 DOI: 10.1136/jech-2016-207982
L. Griffith, P. Raina, M. Levasseur, N. Sohel, H. Payette, H. Tuokko, E. R. van den Heuvel, A. Wister, A. Gilsing, Christopher J. Patterson
Disease-related disability burden: a comparison of seven chronic conditions in middle-aged and older adults.
IF 4.1 3区 材料科学ACS Applied Electronic MaterialsPub Date : 2021-03-23 DOI: 10.1186/s12877-021-02137-6
Chieh-Ying Chou, Ching-Ju Chiu, Chia-Ming Chang, Chih-Hsing Wu, Feng-Hwa Lu, Jin-Shang Wu, Yi-Ching Yang
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Fault latencies of concurrent checking FSMs On the fundamental design gap in terabit per second packet switching Bit-level allocation of multiple-precision specifications Improving mW/MHz ratio in FPGAs pipelined designs Hardware implementation of a memory allocator
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1