Design of low voltage CMOS circuits

Abstract

This article discusses high performance and low-power circuits. It covers leakage control (CAD and circuit techniques) including stacked CMOS with gated-Vdd (application: DRI-cache), multiple VT and dynamic VT, circuit techniques (MTCMOS, VTCMOS. DTMOS, SCMOS, etc.) and SOI implementation. Ultra low voltage digital sub-threshold logic in bursty and non-bursty modes for medical applications, and testing of deep sub-micron low voltage CMOS (modified IDDQ testing and cross-talk faults in high speed circuits) are also discussed.