iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target Environment

Abstract

This paper presents a mechanism which enables verification of algorithmic-level SoC model against actual target environment. By dividing algorithmic SoC model into functional sub-model and interface sub-model and to model the behavior of the latter with FPGA-based in-circuit emulator, we can verify the behavior of the former against actual target environment. The proposed mechanism also include a debugging environment for both functional sub-model and interface sub-model, which enables simultaneous debugging of both hardware and software components of the target SoC model. We implemented H. 264 video encoder and decoder model with the proposed method and verified it against actual target environment.