Shihang Lu, Zhengyu Su, Kaisheng Liao, C. Li, Zhuoling Xiao, Bo Yan, Shuisheng Lin, Bo Wu
{"title":"Receiver System Design for Universal Polyphase DFT Digital Channelization Algorithm","authors":"Shihang Lu, Zhengyu Su, Kaisheng Liao, C. Li, Zhuoling Xiao, Bo Yan, Shuisheng Lin, Bo Wu","doi":"10.1109/icet55676.2022.9825105","DOIUrl":null,"url":null,"abstract":"Receiver plays a vital role in various electronic countermeasure systems and has always been a hot topic to research. Based on the traditional receiver digital channelization structure, this paper further researches and derives the high-efficiency digital channelization structure based on polyphase discrete Fourier transform corresponding to various application scenarios. Then we design a 256-sub-channel digital channelization system and implement it on a 64-channel parallel digital down converter to verify the structure. The system design relies on system on chip as the platform, and we verify the feasibility of it on field programmable gate array.","PeriodicalId":166358,"journal":{"name":"2022 IEEE 5th International Conference on Electronics Technology (ICET)","volume":"387 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 5th International Conference on Electronics Technology (ICET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icet55676.2022.9825105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Receiver plays a vital role in various electronic countermeasure systems and has always been a hot topic to research. Based on the traditional receiver digital channelization structure, this paper further researches and derives the high-efficiency digital channelization structure based on polyphase discrete Fourier transform corresponding to various application scenarios. Then we design a 256-sub-channel digital channelization system and implement it on a 64-channel parallel digital down converter to verify the structure. The system design relies on system on chip as the platform, and we verify the feasibility of it on field programmable gate array.