{"title":"2.4 GHz CMOS VCO design with Verilog-AMS","authors":"Kuo-Hua Cheng, C. Jou","doi":"10.1109/ICM.2003.238421","DOIUrl":null,"url":null,"abstract":"The Verilog-AMS language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. It is an extension to IEEE 1364 Verilog Hardware Description Language (HDL). This paper presents a 2.4 GHz VCO model by Verilog-A for IP and SoC purpose. It fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is 91dBc/HZ@1 MHz offset at 2.4 GHz.","PeriodicalId":180690,"journal":{"name":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2003.238421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The Verilog-AMS language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. It is an extension to IEEE 1364 Verilog Hardware Description Language (HDL). This paper presents a 2.4 GHz VCO model by Verilog-A for IP and SoC purpose. It fabricated by TSMC 0.25-/spl mu/m; based on the measurement results, the tuning range is 187 MHz (7.78%); phase noise is 91dBc/HZ@1 MHz offset at 2.4 GHz.