Simulation and test results of 4-channel low noise rail-to-rail operational amplifier aRD824 based on AD824 prototype

Abstract

A 4-channel low noise rail-to-tail operation amplifier chip aRD824 was developed based on Analog Devices AD824 prototype. The operation amplifier is planned to hold low voltage noise < 4 μV for 0.1 Hz to 10 Hz input, low input bias current < 15 pA, and offset voltage < 0.5 mV. The aRD824 contained modified electric scheme modules of AD824. The modification was initiated by the limitation of the producer “Integral” to obtain proper quality FETs. The electric scheme of aRD824 was simulated in PSpice software, and data were compared to the datasheet of AD824. Simulated signals included – open-loop gain dependence on the signal frequency with no load, small signal response with no load, open-loop gain and small signal response for capacitor load 200 pF, slow rate for 10 kΩ resistance load, input bias current vs. temperature, common-mode rejection vs. frequency, and power supply rejection vs. frequency. A square topology of aRD824 was developed that is more compact than the rectangular topology of AD824. Chips of aRD824 were produced and tested on several performance indicators power supply rejection ratio vs. frequency, small signal response for load 100 pF and 10 kΩ, open loop gain vs. frequency for load 15 pF and 100 kΩ, and output voltage to supply rail vs. sink and source load currents. The measured voltage noise for 0.1 Hz to 10 Hz signal input was 1μV. The experimental results were compared to the datasheet of AD824. A preliminary conclusion was made that aRD824 achieves most of its planned performance parameters and can be accepted as a good analog to AD824. For the final conclusion, additional parameters of aRD824 should be measured to cover all characteristics given in the datasheet of AD824.