Topology-driven cell layout migration with collinear constraints

2009 IEEE International Conference on Computer Design Pub Date : 2009-10-04 DOI:10.1109/ICCD.2009.5413118

De-Shiun Fu, Ying-Zhih Chaung, Yen-Hung Lin, Yih-Lang Li

引用次数: 9

Abstract

Traditional layout migration focuses on area minimization, thus suffered wire distortion, which caused loss of layout topology. A migrated layout inheriting original topology owns original design intention and predictable property, such as wire length which determines the path delay importantly. This work presents a new rectangular topological layout to preserve layout topology and combine its flexibility of handling wires with traditional scan-line based compaction algorithm for area minimization. The proposed migration flow contains devices and wires extraction, topological layout construction, unidirectional compression combining scan-line algorithm with collinear equation solver, and wire restoration. Experimental results show that cell topology is well preserved, and a several times runtime speedup is achieved as compared with recent migration research based on ILP (integer linear programming) formulation.

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具有共线约束的拓扑驱动单元布局迁移

传统的布局迁移注重面积的最小化，导致线材变形，造成布局拓扑的丢失。继承了原拓扑结构的迁移布局具有原有的设计意图和可预测的特性，如导线长度对路径延迟有重要的决定作用。本文提出了一种新的矩形拓扑布局，以保持布局拓扑结构，并将其处理导线的灵活性与传统的基于扫描线的压缩算法相结合，以实现面积最小化。提出的迁移流程包括设备和导线提取、拓扑布局构建、结合扫描线算法和共线方程求解器的单向压缩以及导线恢复。实验结果表明，与基于整数线性规划(ILP)公式的迁移研究相比，该方法可以很好地保留单元的拓扑结构，并且可以实现数倍的运行速度加快。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2009 IEEE International Conference on Computer Design

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