A Low-Power 2-to-7 Modulus Programmable Prescaler with 50% Output Duty Cycle

Ravi Kumar, R. Nagulapalli, Rushikesh Hake, S. Vishvakarma
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Abstract

This paper presents a novel optimized low-power multi-modulus programmable frequency divider with a modulus range of 2-to-7 with 50% output duty cycle for high-speed applications. The proposed divider is demonstrated with the division range from 2-127, which can be extended by adding more stages of the 2/3 Prescaler in the divider chain. The whole design is implemented using $0.18- \mu \mathrm{m}$ CMOS process with a supply of 1.8 V. From simulations result, the proposed design achieves a maximum operating frequency of 5 GHz with 6.5 mW of power consumption in divide-by-127 mode of operation while providing the 50% output duty cycle.
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具有50%输出占空比的低功耗2至7模可编程预分频器
本文提出了一种新型优化的低功耗多模可编程分频器,模量范围为2 ~ 7,输出占空比为50%,适用于高速应用。所提出的分频器的分频范围为2-127,可以通过在分频器链中添加更多的2/3预分频器来扩展。整个设计采用$0.18- \mu \ maththrm {m}$ CMOS工艺,电源为1.8 V。从仿真结果来看,该设计在提供50%的输出占空比的情况下,在除以127的工作模式下实现了5 GHz的最大工作频率和6.5 mW的功耗。
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