An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level

Abstract

As the integration level and clock speed of VLSI devices keep rising, power consumption of those devices increases dramatically. At the same time, shrinking size of transistors that enables denser and smaller chips running at faster clock speeds makes devices more susceptible to environment-induced faults. Both power reduction and concurrent error detection are becoming enabling technologies in Very Deep Sub Micron and nanometer technology domains. However, existing techniques either minimize power of “fault-free” devices, or improve fault tolerance without concerning power. Little work has been proposed to optimize the two objectives simultaneously. In this paper we attack this problem by unifying power efficiency and fault tolerance in a comprehensive Integer Linear Programming formulation. The proposed approach is tested using known benchmarks.