Scalability of Post-Silicon Test Generation for Multi-core RISC-V SOC Validation

Abstract

Instruction Stream Generators (ISG) are an important tool in post-silicon validation of modern CPU s, including RISC- V CPU designs. ISG test generation needs to accurately model the target instruction set and is a compute-intensive process typically performed on off-platform generator machines. With the rising CPU core count and ISA complexity on modern SOC designs, ISG requires a corresponding increase in compute capacity with every generation. The trendline shows that simply throwing more compute at the problem is untenable from a cost perspective. This paper studies several alternative approaches to address this scalability problem. First, it is shown that test generation throughput increases in a nonlinear fashion to an increase in target core count and test length. A correlation curve can be plotted by characterizing test generation throughput against target configurations to identify a sweet spot for test footprint. The study then explores how selective replacement of randomized instruction sequences with fixed routines can improve test generation performance, with careful consideration needed to mitigate any potential loss of validation quality. It then discusses how such test optimizations can even be strategized to improve validation coverage.