On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms

Abstract

Instruction set accelerator architectures have emerged recently as light-weight hardware coprocessors, so as to transparently improve applications performance. This paper investigates the effectiveness of adding hardware accelerators as refers to scaling, based on applications that show data level parallelism such as image edge detection and fractal applications. The implementation results using reconfigurable technology show that, by utilizing a number of hardware coprocessor units, applications such as Sobel edge detection can achieve speedup more than 37Í. Finally, architectural directions based on the developed case studies show that even better performance can be achieved when the overheads of communication, of serialized data accesses, shared memory and of bus protocols are reduced.