Design and evaluation of press-pack SiC MOSFET

Abstract

This paper investigates the advantages of combining press-pack packaging and SiC MOSFETs to extend the application of SiC devices into the high power range. The feasibility of press-pack packaging on SiC MOSFET is illustrated by using extremely small and flexible contact pins called "fuzz buttons" in a low-profile interposer. The layout of the press-pack is designed to have very low main power loop parasitic inductance, gate loop inductance, common source inductance and provide a good balance between paralleled devices. Since the press-pack does not provide internal insulation between the active device and the heatsink, the heatsink is included in the power loop. To minimize the parasitic loop inductance, a water-cooled micro-channel heatsink less than 3 mm thick is used to obtain adequate heat dissipation, electric current carrying capability, and insulation between the cooling loop and the electrical loop. The structure and manufacturing process flow of the press-pack SiC MOSFET are provided. The thermal and electrical performances of the proposed press-pack structure are experimentally tested as well.