Javier Soto Vargas, J. Moreno, J. Madrenas, J. Cabestany
{"title":"Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration","authors":"Javier Soto Vargas, J. Moreno, J. Madrenas, J. Cabestany","doi":"10.1145/3152881.3152885","DOIUrl":null,"url":null,"abstract":"This paper describes a new self-adaptive hardware architecture with fault tolerance capabilities and a development system that allows the creation of applications. This bioinspired architecture is based on an array of cells with capacity for parallel processing, which implements in a distributed way self-adaptive capabilities, like self-routing, self-placement and runtime self-configuration. This cell array together with a component-level routing constitutes a SANE (Self-Adaptive Networked Entity). An integrated development environment and a physical prototype based on two FPGA boards has been built in order to assess the features of the proposed architecture.","PeriodicalId":407032,"journal":{"name":"Proceedings of the 16th Workshop on Adaptive and Reflective Middleware","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 16th Workshop on Adaptive and Reflective Middleware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3152881.3152885","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes a new self-adaptive hardware architecture with fault tolerance capabilities and a development system that allows the creation of applications. This bioinspired architecture is based on an array of cells with capacity for parallel processing, which implements in a distributed way self-adaptive capabilities, like self-routing, self-placement and runtime self-configuration. This cell array together with a component-level routing constitutes a SANE (Self-Adaptive Networked Entity). An integrated development environment and a physical prototype based on two FPGA boards has been built in order to assess the features of the proposed architecture.