Variable throughput LDPC decoders using SIMD-based adaptive quantization

Abstract

In this paper, we present an LDPC decoder design equipped with an adaptive throughput mechanism achievable using a multiple quantization scheme. Three representations are supported by the proposed architecture: 1-bit (hard decision), 2-bit, and 4-bit messages. A throughput increase by of factor of 4, 2 and 1 can be achieved with respect to the 4-bit message representation version, by simultaneously decoding 4, 2, or 1 codewords. This is done by employing a single instruction multiple data (SIMD) approach at processing unit level which is able to process 4, 2 and 1 operands corresponding to the distinct codewords. We provide implementation results for a partial parallel flooding architecture, with serial processing at processing node level. FPGA implementation results indicate that the proposed SIMD approach has an overhead of about 60% in logic with respect to the fixed 4-bit LDPC decoder, with no memory increase, while having a throughput increase of 4× when the hard-decision decoding is used.