Defect tolerance scheme for gigaFLOP WSI architectures

Abstract

Performance is the one area in which a monolithic technology has potential unmatched by other approaches. Integrating an entire high performance system on a single piece of silicon eliminates the off-chip signal delays encountered in multichip implementations, which can become the performance bottleneck in highly pipelined array architectures. The major problem with achieving full wafer integration is that it is virtually impossible to realize such large area circuits entirely defect free. The authors present a scheme which can reconfigure the rectangular array using channel width of 2, while allowing short maximum restructured edge length. The yield of desired array in their design is much higher than that of other designs with same degree of redundancy.<>