A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap

Gyunam Jeon, Yong-Bin Kim
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引用次数: 1

Abstract

This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-capacitors based 1st speculative tap. We propose a quarter-rate DFE to supplement a drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators have not only low input capacitances but also low transconductance (low sensitivity) in order to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages of enough pull-down time because of operating at lower frequency of each data path and widely opened eye diagram at the output. In addition, it consumes less power than the half-rate DFE. The DFE is simulated with 180nm technology node and 1.8V power supply. The S21 parameter (channel loss) is 27 dB at 4 Gbps data rate, and the power consumption is 14.52 mW.
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一个四分之一速率的3分接DFE,用于4Gbps数据速率,基于第一个推测分接的开关容量
本文提出了一种基于开关电容的四分之一速率三分接DFE设计,用于4Gbps数据速率。我们提出了四分之一速率DFE来补充基于开关电容的半速率DFE的缺点。在半速率DFE中,比较器不仅具有低输入电容,而且具有低跨导(低灵敏度),以消除第一个后光标。因此,比较器需要有足够的下拉时间来做出准确的决定。四分之一速率DFE方法由于在每条数据路径的较低频率下工作,并且在输出端打开了较大的眼图,因此具有足够的下拉时间。此外,它比半速率DFE消耗更少的功率。采用180nm工艺节点和1.8V电源对DFE进行仿真。在4gbps数据速率下,S21参数(信道损耗)为27db,功耗为14.52 mW。
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