Loop regularization for image and video processing on instruction level parallel architectures

N. Zingirian, M. Maresca
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Abstract

This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of image and video processing programs running on instruction level parallel (ILP) processors. LR is specifically, devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today's low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique.
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指令级并行结构中图像和视频处理的循环正则化
本文提出了一种新的循环变换(循环正则化,LR),提高了在指令级并行(ILP)处理器上运行的图像和视频处理程序的执行效率。LR是专门为那些不包含指令重排序和寄存器重命名硬件机制的ILP处理器而设计的,例如当今用于嵌入式系统和数字信号处理器的低成本处理器。本文展示了LR的效果,并报告了一组验证该技术的系统级实验。
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