Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875982
Sebastien Vagnier, H. Essafi, A. Mérigot
A content-based information retrieval is well used in many applications (digital libraries, interactive video, medical, ...). The methods involved in content-based information retrieval algorithms need to handle, as quickly as possible, a big volume of data. We are involving in European STRETCH project (Storage and RETrieval by Content of imaged documents) that deals with the archiving and the retrieval by content of imaged (scanned) documents. A component extraction is an important step in the archiving process and it is a time consuming. In this paper we describe a system, based on a configurable processor and a configurable network, designed to accelerate the extraction of the homogeneous components (text, images, table, etc.) of scanned documents.
{"title":"A configurable processor network for document management","authors":"Sebastien Vagnier, H. Essafi, A. Mérigot","doi":"10.1109/CAMP.2000.875982","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875982","url":null,"abstract":"A content-based information retrieval is well used in many applications (digital libraries, interactive video, medical, ...). The methods involved in content-based information retrieval algorithms need to handle, as quickly as possible, a big volume of data. We are involving in European STRETCH project (Storage and RETrieval by Content of imaged documents) that deals with the archiving and the retrieval by content of imaged (scanned) documents. A component extraction is an important step in the archiving process and it is a time consuming. In this paper we describe a system, based on a configurable processor and a configurable network, designed to accelerate the extraction of the homogeneous components (text, images, table, etc.) of scanned documents.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126651967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875969
F. Verdier, A. Mérigot, B. Zavidovique
This paper presents some results of programming efficient matching algorithms on a new asynchronous parallel programming model. Matching algorithms are widely used in image processing when considering high-level treatments. Pattern analysis, database search, 2D and 3D reconstruction all need matching algorithms to perform. Experiments we did were mainly oriented towards a particular matching problem: the stable marriage algorithm. Different implementations of this algorithm have been done on a massively parallel asynchronous model. This model relies on a network of asynchronously communicating processors leading to very fast SIMD treatments. The asynchronous model and implementations of the matching algorithm are presented. An example of image processing problem is also used for illustration purpose and supports the architectural discussion and results.
{"title":"Fast stable matching algorithm using asynchronous parallel programming model","authors":"F. Verdier, A. Mérigot, B. Zavidovique","doi":"10.1109/CAMP.2000.875969","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875969","url":null,"abstract":"This paper presents some results of programming efficient matching algorithms on a new asynchronous parallel programming model. Matching algorithms are widely used in image processing when considering high-level treatments. Pattern analysis, database search, 2D and 3D reconstruction all need matching algorithms to perform. Experiments we did were mainly oriented towards a particular matching problem: the stable marriage algorithm. Different implementations of this algorithm have been done on a massively parallel asynchronous model. This model relies on a network of asynchronously communicating processors leading to very fast SIMD treatments. The asynchronous model and implementations of the matching algorithm are presented. An example of image processing problem is also used for illustration purpose and supports the architectural discussion and results.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129938956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875973
M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot
We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.
{"title":"A system-on-a-chip for pattern recognition architecture and design methodology","authors":"M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot","doi":"10.1109/CAMP.2000.875973","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875973","url":null,"abstract":"We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121400002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875976
Eugene Borovikov, L. Davis
We present a distributed system for constructing volumetric image sequences in real time. Each volumetric image depicts a moving object (e.g., a person) using an octree representation. The object's volume is reconstructed via visual cone intersection using multi-perspective view of the scene.
{"title":"A distributed system for real-time volume reconstruction","authors":"Eugene Borovikov, L. Davis","doi":"10.1109/CAMP.2000.875976","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875976","url":null,"abstract":"We present a distributed system for constructing volumetric image sequences in real time. Each volumetric image depicts a moving object (e.g., a person) using an octree representation. The object's volume is reconstructed via visual cone intersection using multi-perspective view of the scene.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127735398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875981
B. Draper, W. Najjar, Wim Böhm, J. Hammes, Bob Rinker, C. Ross, M. Chawathe, J. Bins
This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.
{"title":"Compiling and optimizing image processing algorithms for FPGAs","authors":"B. Draper, W. Najjar, Wim Böhm, J. Hammes, Bob Rinker, C. Ross, M. Chawathe, J. Bins","doi":"10.1109/CAMP.2000.875981","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875981","url":null,"abstract":"This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127944623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875972
R. Reyna, D. Esteve, D. Houzet, Marie-France Albenge
Based on the statistical learning theory, Support Vector Machines is a novel neural network method for solving image classification problems. It has proven to obtain the optimal decision hyperplane and is also unaware of the dimensionality of the problem. The decision function is constructed with the support vectors obtained during the learning process. Each pixel bloc in the training database is processed as an input vector, the learning process finds out between input vectors those who will construct the solution (the support vectors), the weights and the threshold of the neural network. SVM does not need a test database and the solution depends entirely on the training database. The aim of our work is to exploit the regularities of the SVM decision function in an integrated vision system. The application of our vision system is object detection and localization. We use SVM classifier as the main module of the system. In order to reduce the classification computation time we are proposing a parallel implementation on an FPGA programmed with VHDL.
{"title":"Implementation of the SVM neural network generalization function for image processing","authors":"R. Reyna, D. Esteve, D. Houzet, Marie-France Albenge","doi":"10.1109/CAMP.2000.875972","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875972","url":null,"abstract":"Based on the statistical learning theory, Support Vector Machines is a novel neural network method for solving image classification problems. It has proven to obtain the optimal decision hyperplane and is also unaware of the dimensionality of the problem. The decision function is constructed with the support vectors obtained during the learning process. Each pixel bloc in the training database is processed as an input vector, the learning process finds out between input vectors those who will construct the solution (the support vectors), the weights and the threshold of the neural network. SVM does not need a test database and the solution depends entirely on the training database. The aim of our work is to exploit the regularities of the SVM decision function in an integrated vision system. The application of our vision system is object detection and localization. We use SVM classifier as the main module of the system. In order to reduce the classification computation time we are proposing a parallel implementation on an FPGA programmed with VHDL.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131916835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875975
N. Roma, L. Sousa
Image moments are used in image analysis for object modelling, matching and representation. The computation of high-order moments is a computational intensive task that can not be implemented in real-time with nowadays general-purpose processors. This paper proposes a set of specialised processors for generating an image moment of an arbitrary order in real time, by adopting systolic processing techniques and floating-point arithmetic units. It proposes a modular and cost effective architecture for generating image moments, with a processing time not dependent on the order of the computed moments. The architecture was implemented using different devices, such as programmable digital processors, configurable hardware logic and integrated circuits, by using a 0.7 /spl mu/m CMOS process. The several implementations have shown the effectiveness of the architecture, and the obtained results allow us to compare the different solutions in terms of speed, flexibility, cost and power consumption.
图像矩在图像分析中用于对象建模、匹配和表示。高阶矩的计算是一项计算密集型的任务，目前的通用处理器无法实时实现。本文提出了一套专用处理器，通过采用收缩处理技术和浮点算术单元，实时生成任意顺序的图像矩。它提出了一种模块化和经济有效的结构来生成图像矩，其处理时间不依赖于计算的矩的顺序。该架构采用0.7 /spl μ m CMOS工艺，采用可编程数字处理器、可配置硬件逻辑和集成电路等不同器件实现。几个实现显示了该体系结构的有效性，并且获得的结果允许我们在速度、灵活性、成本和功耗方面比较不同的解决方案。
{"title":"In the development and evaluation of specialized processors for computing high-order 2-D image moments in real-time","authors":"N. Roma, L. Sousa","doi":"10.1109/CAMP.2000.875975","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875975","url":null,"abstract":"Image moments are used in image analysis for object modelling, matching and representation. The computation of high-order moments is a computational intensive task that can not be implemented in real-time with nowadays general-purpose processors. This paper proposes a set of specialised processors for generating an image moment of an arbitrary order in real time, by adopting systolic processing techniques and floating-point arithmetic units. It proposes a modular and cost effective architecture for generating image moments, with a processing time not dependent on the order of the computed moments. The architecture was implemented using different devices, such as programmable digital processors, configurable hardware logic and integrated circuits, by using a 0.7 /spl mu/m CMOS process. The several implementations have shown the effectiveness of the architecture, and the obtained results allow us to compare the different solutions in terms of speed, flexibility, cost and power consumption.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116996528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875980
N. Ratha, Anil K. Jain, D. Rover
In document understanding, one of the early stages involves extracting text strings from a scanned image of the document. Often, the text is printed on a repetitive background of design patterns for visual effects. For recognition purposes, the text strings need to be extracted eliminating the background. Image morphology based algorithms have been proposed for this purpose. However, image morphology operations are compute intensive. We describe the design and synthesis of a high-performance coprocessor to meet the compute load. The algorithm has been synthesized for Splash 2, an attached processor on Sun hosts. The Xilinx Field-Programmable Gate Array (FPGA) based PEs are programmed using VHDL behavioral modeling. The design can run at near-ASIC speeds of /spl ap/22 MHz clock rate with effective timing of 3 milliseconds per 128/spl times/128 image frame and 3/spl times/3 structuring element. Compared with a SPARC station 20 timings of 1.5 sees, the present implementation has a speed advantage of the order of 500 times.
{"title":"FPGA-based coprocessor for text string extraction","authors":"N. Ratha, Anil K. Jain, D. Rover","doi":"10.1109/CAMP.2000.875980","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875980","url":null,"abstract":"In document understanding, one of the early stages involves extracting text strings from a scanned image of the document. Often, the text is printed on a repetitive background of design patterns for visual effects. For recognition purposes, the text strings need to be extracted eliminating the background. Image morphology based algorithms have been proposed for this purpose. However, image morphology operations are compute intensive. We describe the design and synthesis of a high-performance coprocessor to meet the compute load. The algorithm has been synthesized for Splash 2, an attached processor on Sun hosts. The Xilinx Field-Programmable Gate Array (FPGA) based PEs are programmed using VHDL behavioral modeling. The design can run at near-ASIC speeds of /spl ap/22 MHz clock rate with effective timing of 3 milliseconds per 128/spl times/128 image frame and 3/spl times/3 structuring element. Compared with a SPARC station 20 timings of 1.5 sees, the present implementation has a speed advantage of the order of 500 times.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123661925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875977
V. Gesù, B. Lenzitti, Giosuè Lo Bosco, D. Tegolo
The paper shows a distributed architecture for autonomous robot navigation. The architecture is based on three modules that are implemented on separate and interacting agents: the target recognizer, the obsta90cle evaluator and the planner. An adaptive genetic algorithm has been studied to identify mechanisms for reaching the target and for manipulating the 2-directions of the robot; the distributed architecture has been embedded in the DAISY (Distributed Architecture for Intelligent System). Experiments have been carried out using a LEGO intelligent brick.
{"title":"A distributed architecture for autonomous navigation of robots","authors":"V. Gesù, B. Lenzitti, Giosuè Lo Bosco, D. Tegolo","doi":"10.1109/CAMP.2000.875977","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875977","url":null,"abstract":"The paper shows a distributed architecture for autonomous robot navigation. The architecture is based on three modules that are implemented on separate and interacting agents: the target recognizer, the obsta90cle evaluator and the planner. An adaptive genetic algorithm has been studied to identify mechanisms for reaching the target and for manipulating the 2-directions of the robot; the distributed architecture has been embedded in the DAISY (Distributed Architecture for Intelligent System). Experiments have been carried out using a LEGO intelligent brick.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121851021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875964
G. Rovithakis, M. Maniadakis, M. Zervakis
The optimization of Neural Network structures for feature extraction and classification by employing Genetic Algorithms is addressed here. More precisely, a non-linear filter based on High Order Neural Networks (HONN) whose weights are updated by stable learning laws is used to extract the characteristic features of fluorescence spectrums correspond to human tissue samples of different stares. The process is optimized by a generic algorithm which maximizes the separability of different classes. The features are then classified with a Multi-Layer Perceptron (MLP). The high rates of success together with the small time needed to analyze the signals, proves our method very attractive for real time applications.
{"title":"A genetically optimized artificial neural network structure for feature extraction and classification of vascular tissue fluorescence spectrums","authors":"G. Rovithakis, M. Maniadakis, M. Zervakis","doi":"10.1109/CAMP.2000.875964","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875964","url":null,"abstract":"The optimization of Neural Network structures for feature extraction and classification by employing Genetic Algorithms is addressed here. More precisely, a non-linear filter based on High Order Neural Networks (HONN) whose weights are updated by stable learning laws is used to extract the characteristic features of fluorescence spectrums correspond to human tissue samples of different stares. The process is optimized by a generic algorithm which maximizes the separability of different classes. The features are then classified with a Multi-Layer Perceptron (MLP). The high rates of success together with the small time needed to analyze the signals, proves our method very attractive for real time applications.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131111273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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