A 40 Gb/s integrated differential PIN+TIA with DC offset control using InP SHBT technology

D. Caruth, S. Shen, D. Chan, M. Feng, J. Schutt-Ainé
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引用次数: 19

Abstract

Describes the design and measured performance of a 40 Gb/s integrated differential PIN+TIA with offset control using InP SHBT technology. The circuit was designed to handle large average optical input power levels (>5 dBm) encountered in short-haul networks where optical gain control may not be available or economical.
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40gb /s集成差分PIN+TIA,采用InP SHBT技术进行直流偏置控制
介绍了采用InP SHBT技术的40gb /s集成差分PIN+TIA的设计和测量性能。该电路被设计用于处理在短距离网络中遇到的大平均光输入功率电平(> - 5dbm),在这种情况下光增益控制可能不可用或不经济。
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