K. Hu, Houbing Lu, Xu Wang, Feng Li, Xinxin Wang, Tianru Geng, Hang Yang, L. Han, G. Jin
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引用次数: 1
Abstract
We will present a DAQ prototype designed for the ATLAS small-strip Thin Gap Chamber (sTGC) Phase-I trigger upgrade. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 FPGA used for the VMM2 configuration and the events storage, and a Gigabit Ethernet Transceiver (GET) working at the physical layer. The features of the DAQ prototype are described in detail.
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