A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range

Renze Gan, Liangjian Lyu, Geng Mu, C. R. Shi
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Abstract

State-of-the-art capacitively-coupled analog front-end (AFE), which acquire the different frequency band neural signals by adjusting the high-pass cutoff frequency $(\mathrm{f}_{\text{HP}})$, necessitates a tunable gigaohm-level (GO-level) resistor with feedback capacitor to form $\mathrm{f}_{\text{HP}}$. In recent advances [1]–[6], as shown in Fig. 1, there are four means to emulate a GO-level on-chip resistor: 1) conventional pseudo resistor (PR) [1], 2) switched-capacitor resistor (SCR) [2], 3) duty-cycled resistor (DCR) [3], and 4) tunable PR [4]–[6]. By connecting two back-to-back transistors operating in subthreshold region, conventional PR easily realizes the resistance with hundreds of GΩ, but its value varies with PVT over several orders of magnitude. On the contrary, DCR is less sensitive to PVT because its resistance mainly depends on the duty cycle of the clock. However, the maximal achievable resistance of DCR is limited to dozens of GΩ due to the parasitic capacitor. Also, DCR needs an anti-alias filter [2] to avoid noise increasing. A similar dilemma occurring in SCR, although [3] utilizes an SC circuit to attain hundreds-of-GΩ resistance to make the resistor insusceptible to PVT, nonetheless, noise aliasing is a problematic issue to circuit performance in like manner. Compared to DCR and SCR, the tunable PRs proposed in [4]–[6] circumvent noise aliasing due to continuous-time operation. However, to realize a resistor with hundreds of GO, a few picoamperes (pA) bias current $(\mathrm{I}_{\text{BIAS}})$ are required to generate very low VGS in circuit implementation. It is no doubt that a large deviation of resistance of PR will appear due to leakage current. Moreover, to realize the finely tuning of PR in the vicinity of hundreds-of-GΩ resistance, a few picoamperes (pA) bias current with 1 pA adjustment precision may be required, thus, the accuracy of tunable PR is further worsened.
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具有指数可调谐伪电阻和片上数字频率校准环路的神经记录模拟前端,在5- 500 Hz范围内实现高通截止频率的3.4%偏差
最先进的电容耦合模拟前端(AFE)通过调节高通截止频率$(\ mathm {f}_{\text{HP}})$来获取不同频带的神经信号,需要一个可调谐的千兆赫级(go级)电阻和反馈电容来形成$\ mathm {f}_{\text{HP}}$。在最近的进展[1]-[6]中,如图1所示,有四种方法可以模拟go级片上电阻:1)常规伪电阻(PR)[1], 2)开关电容电阻(SCR)[2], 3)占空比电阻(DCR)[3],以及4)可调谐PR[4] -[6]。传统的PR通过连接工作在亚阈值区域的两个背靠背晶体管,很容易实现数百GΩ的电阻,但其值随PVT变化在几个数量级以上。相反,DCR对PVT不太敏感,因为它的电阻主要取决于时钟的占空比。然而,由于寄生电容的原因,DCR的最大可实现电阻限制在数十个GΩ。此外,DCR还需要一个抗混叠滤波器[2]来避免噪声的增加。类似的困境发生在可控硅中,虽然b[3]利用SC电路获得hundreds-of-GΩ电阻,使电阻不受PVT的影响,尽管如此,噪声混叠是电路性能的一个问题。与DCR和可控硅相比,[4]-[6]中提出的可调谐PRs可以避免由于连续工作而产生的噪声混叠。然而,为了实现具有数百个氧化石墨烯的电阻器,在电路实现中需要几皮安(pA)的偏置电流$(\ mathm {I}_{\text{bias}})$来产生非常低的VGS。毫无疑问,由于漏电流的存在,PR的电阻会出现较大的偏差。此外,为了在hundreds-of-GΩ电阻附近实现PR的精细调谐,可能需要几个皮安的偏置电流,调节精度为1 pA,从而进一步降低了可调谐PR的精度。
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