Attacking FPGA-based Dual Complementary AES Implementation Using HD and SD Models

Abstract

Field-programmable gate arrays (FPGAs) are widely used in many fields because of their low power consumption, easy design and good performance. For applications running on FPGAs, security is very important. A lot of researches have been done on the security issue of FPGA implementations, many attacks and countermeasures have been proposed. The dual complementary strategy is a countermeasure designed to thwart side channel attacks. In this paper, we perform Correlation Power Analysis (CPA) against dual complementary AES implemented on the SAKURA-G FPGA board. For dual complementary AES with constant Hamming Weight (HW) value, which is demonstrated to be robust against CPA based on HW model, we successfully recover the secret key using Hamming Distance (HD) and Switching Distance (SD) models with 2,000 power traces. For dual complementary AES with constant HD, 16,000 resp. 10,000 power traces are required to recover the key with HD resp. SD model.