On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study

Abstract

Clock power dissipation has become a significant issue since it occupies around half of the total system power. Due to high working frequency in modern system designs, the transition time of the clock signal is extremely short. In order to keep up with this trend and to use less wire area, a large number of buffers have to be inserted in the network. As a consequence, short-circuit power of the clock buffers is no longer negligible. In this paper, we introduce a methodology which can be applied in global clock tree synthesis to achieve low short-circuit power. It is based on the analysis of any given buffer library in manipulating buffer transition time and hierarchical clustering of loads during buffer insertion. The experimental results are encouraging. Since there are very few works on gate/buffer sizing or buffer library analysis to overcome clocking power problem, we compare our approach with a greedy buffer sizing approach and obtain 13.7% clock power saving for a 10,000 flip-flop design under user-specified clock skew constraints.