Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial

Abstract

In many data converter structures, an embedded digital-to-analog converter (DAC) is a key block, and its mismatch and dynamic errors limit the overall accuracy of the operation. Examples include multi-bit ΔΣ and incremental analog-to-digital converters (ADCs) and successive-approximation-register (SAR) ADCs. In this paper, an overview of existing methods for correcting or mitigating the effects of DAC imperfections is presented. Also, a new foreground digital correction method is described for the mitigation of static mismatch errors in the binary-weighted DAC of a multi-bit ΔΣ or incremental ADC. With minor modifications the correction processes can also be applied to the DAC of a SAR ADC, and the tuning of passive elements used in data converters.