CMOS 90 nm multi-bias transistor model Up to 66 GHz

Abstract

A multi-bias transistor model is proposed in this paper. The nonlinear drain-source current, the output resistance, and the intrinsic capacitance are fully considered to characterize the transistor's bias-dependent performance. On this basis, the values of the model elements are extracted under different bias conditions. Furthermore, a 90 nm CMOS transistor is fabricated and measured to validate the proposed model. The model calculation results are compared with the measurement results, and the root-mean-square error of the model is below 0.007 up to 66 GHz.