A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOS

Pieter A. J. Nuyts, P. Singerl, F. Dielacher, P. Reynaert, W. Dehaene
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引用次数: 40

Abstract

A fully digital up-converter for wireless transmission in the GHz range is presented. The system consists of a polar modulator which uses PWM for the amplitude modulator (AM). Phase modulation (PM) is implemented by shifting the carrier in time. Both the PWM and the PM are implemented using asynchronous delay lines which allow time resolutions down to 10 ps without the need for high-frequent clock signals. The system is designed to drive two class-E power amplifiers with a power combiner. It supports a continuous range of carrier frequencies starting at 946 MHz and limited upwards only by the desired resolution. The modulator has been implemented in 65-nm CMOS. Results show error vector magnitude (EVM) values between 1.24% (−38.1 dB) at 946 MHz and 3.98% (−28.0 dB) at 2.4 GHz for 64-QAM OFDM signals.
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基于全数字延迟线的65纳米CMOS ghz范围多模发射机前端
提出了一种用于GHz频段无线传输的全数字上变频器。该系统由一个极性调制器组成,该调制器使用PWM作为调幅器(AM)。相位调制(PM)是通过及时移动载波来实现的。PWM和PM都是使用异步延迟线实现的,允许时间分辨率低至10 ps,而不需要高频时钟信号。该系统设计用于驱动两个e类功率放大器和一个功率合成器。它支持从946 MHz开始的连续载波频率范围,并且仅受所需分辨率的限制。该调制器已在65纳米CMOS上实现。结果表明,64-QAM OFDM信号在946 MHz时的误差矢量幅度(EVM)为1.24%(−38.1 dB),在2.4 GHz时为3.98%(−28.0 dB)。
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