A Novel Mini-LVDS Receiver in 0.35-um CMOS

2006 IEEE International SOC Conference Pub Date : 1900-01-01 DOI:10.1109/ICSICT.2006.306270

Chung-Yuan Chen, Jia-Hong Wang, T. Sun

引用次数: 1

Abstract

This paper presents the design of receiver circuits for flat-plane application. Due to the differential transmission technique and the low voltage swing, mini-LVDS (low-voltage differential signaling) allows high transmission speeds and low power consumption at the same time. In the proposed receiver, high transmission speed with the minimum common-mode and differential voltage at the input for mini-LVDS application was achieved. The circuit was designed in a 3.3-V 0.35- mum CMOS technology, and the transmission operations is more than 500 Mb/s with random data patterns. The total power consumption is 3.5 mW.

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

一种新型的0.35微米CMOS微型lvds接收器

本文介绍了平面应用的接收电路设计。由于差分传输技术和低电压摆幅，mini-LVDS(低压差分信号)可以同时实现高传输速度和低功耗。在该接收机中，实现了以最小的共模和差分电压输入的高传输速度，适用于微型lvds应用。电路采用3.3 v 0.35 μ m CMOS技术设计，传输速度大于500mb /s，数据模式随机。总功耗为3.5 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文去求助

来源期刊

2006 IEEE International SOC Conference

自引率

0.00%

发文量

期刊最新文献

Architecture for Energy Efficient Sphere Decoding Design of Low Power Digital Phase Lock Loops A Novel 8-Phase PLL Design for PWM Scheme in High Speed I/O Circuits Interrupt Communication on the SegBus platform A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design