A Hardware-Software Co-design for H.264/AVG Decoder

Abstract

A single chip decoder SOC for H.264 baseline profile, called OR264 (OR1K based H264 decoder), is presented in this paper. The chip has mixed hardware/software architecture to combine performance and flexibility. It is partitioned that the hardware is used to boost the performance and efficiency of key operations in H.264 decoder while the software is used to control the decoding flow and to synchronize the hardware modules. All hardware units operate in parallel. The hardware can decode a MB in 851 clock cycles under ideal condition. The chip is fabricated using UMC 0.18-mum 6-layers metal CMOS process. It contains 1.5 M transistors and 176k bits embedded SRAM. The die size is 4.8 mm x 4.8 mm and the critical path is 10 ns.