On the Design of High Performance RF Integrated Inductors on High Resistively Thin Film 65 nm SOI CMOS Technology

Abstract

During past years, High Resistivity (HR) SOI CMOS technology has emerged as a promising one for the integration of RF applications, mainly because of the improvement of passive component related to HR substrate. This paper summarizes, for the first time, an in depth analysis of different optimization scheme suitable for on-chip inductors fabricated on HR substrate, using advanced 65 nm SOI CMOS technology with 6 copper metal levels. Measurement results demonstrated that proposed optimized SOI inductor architectures, integrated in a standard advanced digital back-end of line (BEOL), could address high quality factor (single ended quality factor greater than 20), have high current capability (up to 260 mA @ 125degC) or could enable a huge area saving (up to 50 %).