55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter

Tzu-Chi Huang, W. Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Y. Peng, F. Hsueh
{"title":"55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter","authors":"Tzu-Chi Huang, W. Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Y. Peng, F. Hsueh","doi":"10.1109/ESSCIRC.2011.6044987","DOIUrl":null,"url":null,"abstract":"This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044987","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

Abstract

This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
55nm CMOS 12位250MHz数模转换器,采用动态电压缩放(DVS)技术,通过单电感双输出(SIDO)转换器
这款55nm CMOS 12位电流转向DAC直接由单电感双输出(SIDO)开关DC-DC转换器和动态电压缩放(DVS)技术供电,将DAC的功率效率提高了25%,SFDR达到65.34dB。提出的3S方法,包括分离、分裂和移位,有效地将电流失配降低到0.2%以内,并抑制了SIDO转换器的开关噪声干扰。与传统方法相比,12位DAC和SIDO模块实现了兼容的性能,并且具有面积和能源效率的优点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
A precision DTMOST-based temperature sensor 8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-Bias A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1