Two dimensional systolic adaptive DLMS FIR filters for image processing on FPGA

Abstract

The aim of this paper is to hardware description and implementing of adaptive digital one- dimensional (1-D) and two-dimensional (2-D) Finite Impulse Response (FIR) filters on Field Programmable Gate Array (FPGA) technology. The 2-D adaptive filter is particularly employed for image processing applications and a typical adaptive image noise cancellation application is considered. The delayed least mean square (DLMS) algorithm is used for updating filter weights in dynamic unknown environments. Some cell processors consisting a tree based systolic architecture are employed for improving speed of proposed 2-D filter for noisy image processing. The VHDL hardware description language is employed for modeling and hardware description of different schemes of filtering applications. The obtained results from the QUARTUS II tool on STRATIX II EP2S15F484C3 chip from ALTERA Inc. demonstrate a satisfactory performance of 2-D adaptive FIR filter for image noise cancellation in some wellknown image test-bench.