{"title":"Design of a multistage decimation-interpolation filter","authors":"V. Hansen","doi":"10.1109/ICASSP.1987.1169830","DOIUrl":null,"url":null,"abstract":"A 2 chip digital multi-rate FIR filter implemented in 2 micron CMOS performs 10 million multiplications and 20 million accumulations per second. The filter has 48 programmable bandwidths in a 1-2-5 sequence, and can either interpolate or decimate. This paper describes the design and implementation of the filter.","PeriodicalId":140810,"journal":{"name":"ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASSP.1987.1169830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 2 chip digital multi-rate FIR filter implemented in 2 micron CMOS performs 10 million multiplications and 20 million accumulations per second. The filter has 48 programmable bandwidths in a 1-2-5 sequence, and can either interpolate or decimate. This paper describes the design and implementation of the filter.
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