C. Xu, P. Batude, M. Vinet, M. Mouis, M. Cassé, B. Sklénard, B. Colombeau, Q. Rafhay, C. Tabone, J. Berthoz, B. Previtali, J. Mazurier, L. Brunet, L. Brevard, F. Khaja, J. Hartmann, F. Allain, A. Toffoli, R. Kies, C. Le Royer, S. Morvan, A. Pouydebasque, X. Garros, A. Pakfar, C. Tavernier, O. Faynot, T. Poiroux
{"title":"Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length","authors":"C. Xu, P. Batude, M. Vinet, M. Mouis, M. Cassé, B. Sklénard, B. Colombeau, Q. Rafhay, C. Tabone, J. Berthoz, B. Previtali, J. Mazurier, L. Brunet, L. Brevard, F. Khaja, J. Hartmann, F. Allain, A. Toffoli, R. Kies, C. Le Royer, S. Morvan, A. Pouydebasque, X. Garros, A. Pakfar, C. Tavernier, O. Faynot, T. Poiroux","doi":"10.1109/VLSI-TSA.2012.6210171","DOIUrl":null,"url":null,"abstract":"For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210171","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.
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