Failure Analysis Methodology on Systematic MIM failure in Wafer Fabrication

Abstract

In this paper, a low yield case relating to IDD leakage at active mode due to the systematic breakdown signature consistently at the top MIM edge was studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP probing, layout path tracing, FIB circuit edit, SEM XTEM and top down PFA methodology together with Fab investigation are used to understand the root cause as well as failure mechanism. This paper highlights that there are 2 types of leakage (high leakage in mA and low leakage in uA). The high leakage dies revealed spot directly at the MIM cap and anomaly can be observed at the MIM edge. However, for the low level leakage, hotspot was seen at the PMOS transistor and NOT at the MIM Cap. Besides layout tracing that enable to pinpoint the suspected MIM cap, 2 types of simulation (Intentionally induced damage and FIB Circuit Edit) were performed to prove and validate the MIM defect is the only root cause for this low yield issue and the RF circuitry has no contribution to it. Additionally, top down PFA methodology was engaged to reveal the physical evidence of the damage at the edge of the MIM. This confirmed that both type of leakage are due to similar MIM breakdown issue.