FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186) Pub Date : 1997-04-16 DOI:10.1109/FPGA.1997.624615

Roger Francis Woods, S. Ludwig, J. Heron, D. Trainor, Stephan W. Gehring

引用次数: 6

Abstract

The implementation of a number of FIR filter structures in the Xilinx XC6200 technology is presented. The designs have been implemented using a combination of IRIS, an architectural synthesis tool and Trianus/Hades a set of integrated tools for implementing algorithms on Custom Computing Machines. The main attraction of this approach is that it allows algorithms to be compiled quickly allowing performance changes to be made at the architectural level in IRIS rather than at the FPGA layout level.

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在XC6200上使用IRIS和Trianus/Hades(或从天堂到地狱再回来)的FPGA合成

介绍了几种FIR滤波器结构在Xilinx XC6200技术上的实现。这些设计已经使用IRIS(一个架构综合工具)和Trianus/Hades(一组用于在自定义计算机上实现算法的集成工具)的组合来实现。这种方法的主要吸引力在于它允许快速编译算法，从而允许在IRIS的体系结构级别而不是在FPGA布局级别进行性能更改。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

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