Electromigration in advanced Bond Pad structures

Ki-Don Lee
{"title":"Electromigration in advanced Bond Pad structures","authors":"Ki-Don Lee","doi":"10.1109/IRPS.2013.6532077","DOIUrl":null,"url":null,"abstract":"VIATOP (VT), Aluminum Via connecting the bond pad and the Top Copper level, is the critical component for Bond Pad (BP) Electromigration (EM) in advanced technology nodes, where a smaller VT or its array is employed for maximum chip-scaling. In this study, we evaluated BP EM using various dimensions of VT, investigated the scaling effect, and proposed a BP EM model for current crowding & reservoir effect in the VT.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"312 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2013.6532077","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

VIATOP (VT), Aluminum Via connecting the bond pad and the Top Copper level, is the critical component for Bond Pad (BP) Electromigration (EM) in advanced technology nodes, where a smaller VT or its array is employed for maximum chip-scaling. In this study, we evaluated BP EM using various dimensions of VT, investigated the scaling effect, and proposed a BP EM model for current crowding & reservoir effect in the VT.
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先进键合垫结构中的电迁移
VIATOP (VT),铝制通过连接键合垫和顶部铜位,是先进技术节点中键合垫(BP)电迁移(EM)的关键组件,其中采用较小的VT或其阵列以实现最大的芯片缩放。在本研究中,我们使用VT的不同维度来评估BP EM,研究了尺度效应,并提出了VT中电流拥挤和储层效应的BP EM模型。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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