Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic

Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784) Pub Date : 2004-09-04 DOI:10.1145/1016568.1016619

Mário C. B. Osorio, Carlos A. Sampaio, A. Reis, R. Ribas

引用次数: 18

Abstract

This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable/disable CMOS differential logic (MOECDL) style. The MOECDL structure proposed represents a promising technique for iterative networks and self-timed circuits. The recursive property of CLA algorithm has been efficiently exploited to demonstrate the advantages of multiple-output structures. The 32-bit MOECDL CLA circuit has been designed into a standard 0.5 /spl mu/m CMOS technology. Comparison to the known DCVS style is presented through electrical simulation.

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使用多输出使能-禁用 CMOS 差分逻辑的增强型 32 位进位前瞻加法器

本文介绍了一种使用多输出使能/禁用 CMOS 差分逻辑（MOECDL）方式实现的增强型 32 位进位前瞻（CLA）加法器。所提出的 MOECDL 结构是一种很有前途的迭代网络和自定时电路技术。我们有效地利用了 CLA 算法的递归特性，展示了多输出结构的优势。32 位 MOECDL CLA 电路采用标准 0.5 /spl mu/m CMOS 技术设计。通过电气仿真与已知的 DCVS 方式进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)

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