Use of multiple numeration systems for architecture and design of a high performance FIR filter netlist generator

Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004. Pub Date : 2004-12-06 DOI:10.1109/ICM.2004.1434721

L. Noury, H. Mehrez, F. Durbin, Tissot A

引用次数: 3

Abstract

With increased complexity and shorter development cycle of hardware, designers cannot afford to redesign similar subcomponents. They have to focus on the global design, and must extract a validated netlist from the specification of some classic component, thus insuring good performance and adaptation to their needs. In this paper, we present the design methodology for a FIR filter netlist generator, the FIR filter being one of the most frequently used device in digital signal processing. Starting from mathematical equation and specification parameters, we include arithmetic knowledge in the generator, allowing architecture choices based on filter properties and realistic parameters values. We also provide a rounding option and a validation framework.

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利用多个计数系统的架构和设计一个高性能FIR滤波器网表生成器

随着硬件复杂性的增加和开发周期的缩短，设计人员无法重新设计类似的子组件。他们必须关注全局设计，并且必须从某些经典组件的规范中提取经过验证的网络列表，从而确保良好的性能并适应他们的需求。本文介绍了一种FIR滤波器网表发生器的设计方法，FIR滤波器是数字信号处理中最常用的器件之一。从数学方程和规格参数出发，我们在生成器中加入了算术知识，允许基于滤波器属性和实际参数值的架构选择。我们还提供了舍入选项和验证框架。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.

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