Using of Integrated Daemon Module for Internal Processing Cells Addressing in Systolic Architecture

Abstract

FPGA programmable logic devices make it possible to implement known and synthesize new architectures with many applications. Increasingly, these implementations are based on systolic array that combine very good capabilities and features. The article discusses a method for shortening additional resource for change of a specific parametric value in a given computing element of the systolic architecture by embedding a small single-register module in each cell.