Complete testing of receiver jitter tolerance

Abstract

Devices incorporating high-speed digital receivers must tolerate timing instability. The ability of the receiver to correctly place a receive strobe within the data valid region of a bit fundamentally determines the bit error rate performance for a design or a particular device. The device must meet its performance requirements in the presence of non-ideal timing. Timing irregularities can be introduced from additive non-deterministic noise sources injecting random jitter (Rj); deterministic distortion such as a limited channel bandwidth injecting data dependent jitter (DDj) or circuit oscillations and coupled clocks injecting periodic jitter (Pj).