Using a formal specification and a model checker to monitor and direct simulation

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451) Pub Date : 2003-06-02 DOI:10.1145/775832.775926

S. Tasiran, Yuan Yu, Brannon Batson

引用次数: 22

Abstract

We describe a technique for verifying that a hardware design correctly implements a protocol-level format specification. Simulation steps are translated to protocol state transitions using a refinement map and then verified against the specification using a model checker. On the specification state space, the model checker collects coverage information and identifies states violating certain properties. It then generates protocol-level traces to these coverage gaps and error states. This technique was applied to the multiprocessing hardware of the Alpha 21364 microprocessor and the cache coherence protocol. We were able to generate an error trace which exercised a bug in the implementation that had not been discovered before a prototype was built.

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使用正式的规范和模型检查器来监视和指导模拟

我们描述了一种验证硬件设计是否正确实现协议级格式规范的技术。使用细化映射将模拟步骤转换为协议状态转换，然后使用模型检查器根据规范进行验证。在规范状态空间上，模型检查器收集覆盖信息并识别违反某些属性的状态。然后，它生成对这些覆盖缺口和错误状态的协议级跟踪。该技术应用于Alpha 21364微处理器的多处理硬件和缓存一致性协议。我们能够生成一个错误跟踪，它执行了在原型构建之前未被发现的实现中的错误。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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