{"title":"A 100-MHz 256b-I/O 1-Mb planar nonvolatile STT-MRAM with novel memory cells","authors":"Rui Wang, H. Dery, Michael C. Huang, Hui Wu","doi":"10.1109/NVMTS.2016.7781511","DOIUrl":null,"url":null,"abstract":"This paper presents a 1Mb STT-MRAM consisting of novel planar memory cells with built-in differential voltage output. Each memory cell contains four planar ferromagnets, one PMOS and one NMOS to enable read operation, one NMOS to enable write operation and four transmission gates to pass write current in opposite directions. The output differential voltage of two read contacts in each memory cell is 23.66 mV for logic '1' and only 0.46 mV for logic '0', which renders high signal-to-noise ratio. Estimated area of each memory cell in 65-nm CMOS technology is 1.5 um2 (355 F2). The proposed 1Mb STT-MRAM consumes dynamic write power of 12.8 mW, static leakage power of 4mW and dynamic read power of 11.10 mW to achieve 100MHz operation.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NVMTS.2016.7781511","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents a 1Mb STT-MRAM consisting of novel planar memory cells with built-in differential voltage output. Each memory cell contains four planar ferromagnets, one PMOS and one NMOS to enable read operation, one NMOS to enable write operation and four transmission gates to pass write current in opposite directions. The output differential voltage of two read contacts in each memory cell is 23.66 mV for logic '1' and only 0.46 mV for logic '0', which renders high signal-to-noise ratio. Estimated area of each memory cell in 65-nm CMOS technology is 1.5 um2 (355 F2). The proposed 1Mb STT-MRAM consumes dynamic write power of 12.8 mW, static leakage power of 4mW and dynamic read power of 11.10 mW to achieve 100MHz operation.