Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781511
Rui Wang, H. Dery, Michael C. Huang, Hui Wu
This paper presents a 1Mb STT-MRAM consisting of novel planar memory cells with built-in differential voltage output. Each memory cell contains four planar ferromagnets, one PMOS and one NMOS to enable read operation, one NMOS to enable write operation and four transmission gates to pass write current in opposite directions. The output differential voltage of two read contacts in each memory cell is 23.66 mV for logic '1' and only 0.46 mV for logic '0', which renders high signal-to-noise ratio. Estimated area of each memory cell in 65-nm CMOS technology is 1.5 um2 (355 F2). The proposed 1Mb STT-MRAM consumes dynamic write power of 12.8 mW, static leakage power of 4mW and dynamic read power of 11.10 mW to achieve 100MHz operation.
{"title":"A 100-MHz 256b-I/O 1-Mb planar nonvolatile STT-MRAM with novel memory cells","authors":"Rui Wang, H. Dery, Michael C. Huang, Hui Wu","doi":"10.1109/NVMTS.2016.7781511","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781511","url":null,"abstract":"This paper presents a 1Mb STT-MRAM consisting of novel planar memory cells with built-in differential voltage output. Each memory cell contains four planar ferromagnets, one PMOS and one NMOS to enable read operation, one NMOS to enable write operation and four transmission gates to pass write current in opposite directions. The output differential voltage of two read contacts in each memory cell is 23.66 mV for logic '1' and only 0.46 mV for logic '0', which renders high signal-to-noise ratio. Estimated area of each memory cell in 65-nm CMOS technology is 1.5 um2 (355 F2). The proposed 1Mb STT-MRAM consumes dynamic write power of 12.8 mW, static leakage power of 4mW and dynamic read power of 11.10 mW to achieve 100MHz operation.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133110617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781513
Swatilekha Majumdar, Sandeep Kaur Kingra, M. Suri, M. Tikyani
In this paper, we present an OxRAM based compact 4T-2R NVSRAM design with a novel efficient programming scheme to achieve low-power and low area footprint. 3 nm thick HfOx based OxRAM devices and 90 nm CMOS technology node were used for all simulations. Our proposed 4T-2R NVSRAM is programmed using a two cycle write process and is implemented for real-time non-volatility rather than last-bit, or power-down non-volatility. We also show that by carefully choosing the OxRAM programmed resistance levels the pull-down NMOS transitor size, and NVSRAM programming energy can be further reduced by a factor of 3x and 4x respectively.
{"title":"Hybrid CMOS-OxRAM based 4T-2R NVSRAM with efficient programming scheme","authors":"Swatilekha Majumdar, Sandeep Kaur Kingra, M. Suri, M. Tikyani","doi":"10.1109/NVMTS.2016.7781513","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781513","url":null,"abstract":"In this paper, we present an OxRAM based compact 4T-2R NVSRAM design with a novel efficient programming scheme to achieve low-power and low area footprint. 3 nm thick HfOx based OxRAM devices and 90 nm CMOS technology node were used for all simulations. Our proposed 4T-2R NVSRAM is programmed using a two cycle write process and is implemented for real-time non-volatility rather than last-bit, or power-down non-volatility. We also show that by carefully choosing the OxRAM programmed resistance levels the pull-down NMOS transitor size, and NVSRAM programming energy can be further reduced by a factor of 3x and 4x respectively.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117299198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781514
Bonan Yan, Zheng Li, Yiran Chen, Hai Helen Li
Spin-transfer torque magnetic random access memory (STT-MRAM) is a prospective candidate for cache and main memory designs. However, the reliable revision of magnetization using current requires high current density, which is hardly affordable in aggressive scaling-down technology node. Nanoring shaped magnetic tunneling junction (NR-MTJ) remarkably reduces STT programming current density, as indicated by theoretical analysis. In this paper, we first introduce the fundamental of STT technology and describe the NR-MTJ's structure and characteristics. The design and implementation of a 4Kb STTMRAM with NR-MTJs, and a TCAM design for high speed and robustness are then demonstrated.
{"title":"RAM and TCAM designs by using STT-MRAM","authors":"Bonan Yan, Zheng Li, Yiran Chen, Hai Helen Li","doi":"10.1109/NVMTS.2016.7781514","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781514","url":null,"abstract":"Spin-transfer torque magnetic random access memory (STT-MRAM) is a prospective candidate for cache and main memory designs. However, the reliable revision of magnetization using current requires high current density, which is hardly affordable in aggressive scaling-down technology node. Nanoring shaped magnetic tunneling junction (NR-MTJ) remarkably reduces STT programming current density, as indicated by theoretical analysis. In this paper, we first introduce the fundamental of STT technology and describe the NR-MTJ's structure and characteristics. The design and implementation of a 4Kb STTMRAM with NR-MTJs, and a TCAM design for high speed and robustness are then demonstrated.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132234476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memory unit, especially the non-volatile memory (NVM), is an indispensable component in a high performance electronic systems which aims at efficient information processing and storage. Resistive random access memory (RRAM) is one of the most promising candidates among the emerging memory technologies. However, optimization of the variability introduced by the intrinsic stochastic nature of filament formation remains a tough problem. In this paper, both operation voltage and resistance of the device with localized implantation show significant improvement of uniformity compared with uniformly doped device, which can be attributed to the further undermine of the randomness due to localized doping instead of uniformly doping.
{"title":"Localized metal doping effect on switching behaviors of TaOx-based RRAM device","authors":"Zongwei Wang, Jian Kang, Yichen Fang, Zhizhen Yu, Xue Yang, Yimao Cai, Yangyuan Wang, Ru Huang","doi":"10.1109/NVMTS.2016.7781516","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781516","url":null,"abstract":"Memory unit, especially the non-volatile memory (NVM), is an indispensable component in a high performance electronic systems which aims at efficient information processing and storage. Resistive random access memory (RRAM) is one of the most promising candidates among the emerging memory technologies. However, optimization of the variability introduced by the intrinsic stochastic nature of filament formation remains a tough problem. In this paper, both operation voltage and resistance of the device with localized implantation show significant improvement of uniformity compared with uniformly doped device, which can be attributed to the further undermine of the randomness due to localized doping instead of uniformly doping.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133141747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781510
Jang-Woo Ryu, K. Kwon
This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.
{"title":"A self-reference sensing for improving reliability and bandwidth with 2T2MTJ STT-MRAM cell","authors":"Jang-Woo Ryu, K. Kwon","doi":"10.1109/NVMTS.2016.7781510","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781510","url":null,"abstract":"This paper presents a self-reference read scheme with 2T2MTJ STT-MRAM static gain cell which improves sensing margin and operating speed enough to replace the on-die cache memories and the embedded applications. The proposed self-reference sensing scheme completely suppresses variations and mismatches in MTJs and circuits. The performance is evaluated with the Verilog-A MTJ model and the Monte-Carlo analysis in 65nm CMOS process technology. The proposed circuits show 100mV sensing margin in 5ns tCK, 0.8V VDD and 100% TMR.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"2019 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781517
J. Müller, P. Polakowski, S. Müller, H. Mulaosmanovic, J. Ocker, T. Mikolajick, S. Slesazeck, S. Flachowsky, M. Trentzsch
In this paper potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed. These pathways are based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectric-insulator-semiconductor gate stack are the dominant degradation mechanisms during program and erase operation. Three different approaches capable of lowering or eliminating the interfacial field stress are being assessed - lowering the electrical field stress induced by polarization reversal; utilizing low voltage sub-loop operation; altering the capacitive divider within the gate stack.
{"title":"High endurance strategies for hafnium oxide based ferroelectric field effect transistor","authors":"J. Müller, P. Polakowski, S. Müller, H. Mulaosmanovic, J. Ocker, T. Mikolajick, S. Slesazeck, S. Flachowsky, M. Trentzsch","doi":"10.1109/NVMTS.2016.7781517","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781517","url":null,"abstract":"In this paper potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed. These pathways are based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectric-insulator-semiconductor gate stack are the dominant degradation mechanisms during program and erase operation. Three different approaches capable of lowering or eliminating the interfacial field stress are being assessed - lowering the electrical field stress induced by polarization reversal; utilizing low voltage sub-loop operation; altering the capacitive divider within the gate stack.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117350840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781512
A. Kumar, M. Suri, V. Parmar, N. Locatelli, D. Querlioz
We propose a novel writing scheme for hybrid CMOSMTJ TCAM cells to achieve low write energy for approximate computing applications, by exploiting the noise tolerant behavior of such computational paradigms. We show that by exploiting stochastic MTJ switching TCAM cell write energy and latency can be improved. In particular, for an n-bit TCAM, used for approximate computing application, the least significant bits (LSBs) can be operated with weak stochastic write conditions without a significant drop on match accuracy. Distance match accuracy for a 3-bit (LSB), 4T-2MTJ TCAM, designed using 90 nm CMOS technology node and 57 nm (diameter) perpendicular magnetic anisotropic (PMA) MTJ devices was investigated. Using a write probability of 0.97, the overall write energy per LSB was decreased by a factor of 2.3 x, while keeping the cell write latency 7 ns. Impact of MTJ device variability on TCAM cell parameters such as search noise margin (NM) was also analyzed.
{"title":"An energy-efficient hybrid (CMOS-MTJ) TCAM using stochastic writes for approximate computing","authors":"A. Kumar, M. Suri, V. Parmar, N. Locatelli, D. Querlioz","doi":"10.1109/NVMTS.2016.7781512","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781512","url":null,"abstract":"We propose a novel writing scheme for hybrid CMOSMTJ TCAM cells to achieve low write energy for approximate computing applications, by exploiting the noise tolerant behavior of such computational paradigms. We show that by exploiting stochastic MTJ switching TCAM cell write energy and latency can be improved. In particular, for an n-bit TCAM, used for approximate computing application, the least significant bits (LSBs) can be operated with weak stochastic write conditions without a significant drop on match accuracy. Distance match accuracy for a 3-bit (LSB), 4T-2MTJ TCAM, designed using 90 nm CMOS technology node and 57 nm (diameter) perpendicular magnetic anisotropic (PMA) MTJ devices was investigated. Using a write probability of 0.97, the overall write energy per LSB was decreased by a factor of 2.3 x, while keeping the cell write latency 7 ns. Impact of MTJ device variability on TCAM cell parameters such as search noise margin (NM) was also analyzed.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115841090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-10-01DOI: 10.1109/NVMTS.2016.7781515
S. Slesazeck, M. Herzig, T. Mikolajick, A. Ascoli, M. Weiher, R. Tetzlaff
Threshold switching effects in niobium oxide based filamentary resistance switching devices have attracted increasing attention due to their potential to realize scalable selector devices for ReRAM. For an application in large scale arrays the device-to-device variability is of major importance. In our work we developed a physical model describing the threshold switching effect based on a Frenkel-Poole like conduction mechanism. Based on the model we analyze the source of variability of the threshold voltage Vth in the threshold switching effect of the NbOx based devices. In particular, we investigate, to which extent the inherent coexisting non-volatile memory switching effect or the thermal properties of the threshold switch are responsible for the variability of the threshold voltage.
{"title":"Analysis of Vth variability in NbOx-based threshold switches","authors":"S. Slesazeck, M. Herzig, T. Mikolajick, A. Ascoli, M. Weiher, R. Tetzlaff","doi":"10.1109/NVMTS.2016.7781515","DOIUrl":"https://doi.org/10.1109/NVMTS.2016.7781515","url":null,"abstract":"Threshold switching effects in niobium oxide based filamentary resistance switching devices have attracted increasing attention due to their potential to realize scalable selector devices for ReRAM. For an application in large scale arrays the device-to-device variability is of major importance. In our work we developed a physical model describing the threshold switching effect based on a Frenkel-Poole like conduction mechanism. Based on the model we analyze the source of variability of the threshold voltage Vth in the threshold switching effect of the NbOx based devices. In particular, we investigate, to which extent the inherent coexisting non-volatile memory switching effect or the thermal properties of the threshold switch are responsible for the variability of the threshold voltage.","PeriodicalId":228005,"journal":{"name":"2016 16th Non-Volatile Memory Technology Symposium (NVMTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126965233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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